The electrically erasable programmable read-only memo (hereinafter referred to as EEPROM) has proven useful because it combines the convenience of non-volatile data storage with the capability to erase the stored data electrically, then program new data. The utility of EEPROM has been increased by the development of various types of flash EEPROM, which erase a large number of memory cells simultaneously. There is a strong interest in flash EEPROM with megabit storage capacity for use in devices such as portable computers.
The basic EEPROM memory cell has a field-effect transistor with a control gate and a floating gate. The cell is erased and programmed by producing a potential difference between the control gate and the source or drain large enough to cause Fowler-Nordheim tunneling of electrons into or out of the floating gate. A high voltage required for the tunneling is generated within the EEPROM chip.
For example, one prior-art EEPROM has a charge pump by which it generates 20 V internally, using the potential difference between this voltage and ground (0 V) for erasing and programming. Another prior-art EEPROM has a negative charge pump that generates xe2x88x9215 V internally, using the 20 V potential difference between this and the 5 V supply voltage for erasing and programming. Still another prior-art EEPROM produces 18 V and xe2x88x9211 V internally, using the potential difference between xe2x88x9211 V and the supply voltage (5 V) for erasing and the potential difference between 18 V and ground (0 V) for programming.
A problem with these prior-art EEPROMs is that the transistors that deliver voltages such as 20 V, 18 V, xe2x88x9211 V and xe2x88x9215 V to the memory cell must be large in size. To provide high breakdown voltages, these transistors require deep junctions and thick gate oxides, or increased gate lengths. Occupying excessive space on the EEPROM chip, they make it difficult to attain the high levels of integration desired for many applications.
A related problem is that longer-than-normal wafer processes are needed to fabricate these high-voltage transistors. Thus they add to the time and cost of the EEPROM manufacturing process.
A further problem, particularly in flash EEPROMs that erase all memory cells simultaneously, is that delivery of a high erasing voltage to a memory cell that is already erased can drive the floating gate of the memory cell into a depletion mode, causing the cell to leak and produce false data. Complex schemes have been necessary to avoid such overerasing.
It is accordingly an object of the present invention to reduce the voltages required for erasing and programming EEPROM memory cells.
Another object of the invention is to reduce the size of driver transistors for EEPROM word lines and bit lines.
Still another object is to reduce the size of select transistors in EEPROM memory cells.
Yet another object is to shorten the EEPROM fabrication process.
A further object is to avoid the problem of overerasing EEPROM memory cells.
The invented method of erasing and programming an EEPROM memory cell uses a supply voltage and a ground voltage to generate a first voltage higher than both the supply voltage and the ground voltage, and a second voltage lower than both the supply voltage and the ground voltage. The memory cell comprises a nonvolatile storage transistor having a floating gate. To erase the memory cell, the first voltage is applied on a first side of the floating gate electrode of the nonvolatile storage transistor and the second voltage is applied on a second side of the floating gate, opposite to the first side. To program the memory cell, the second voltage is applied on the first side of the floating gate, and the first voltage is applied on the second side of the floating gate.